The present invention relates methods and apparatus for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) technologies.
In partially depleted silicon-on-insulator (SOI) technologies, it is often desirable or required to create P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) body connections. Typically external metal contacts are used for such FET body connections. External body contacts are very area costly. One body contact per device can easily increase a cell layout area by 50% to 100%.
External body contacts are often sources of parameter mismatches, which are undesirable for dual-railed or differential type of circuits that require parameter matching. The quality of body contacts is very difficult to control in the fabrication process. There are many factors that affect matching quality of devices, such as, ohmic contact quality of the body contacts, bias-dependent body (sheet) resistivity, and uncertainty in the number of physical layout squares along the length of the body when making body contacts.
Also adding external body contacts may destroy the on-pitch layout property due to width expansion in either or both x and y dimensions. A drawback of making external body contacts is that easy design migration and efficient use of existing design data are prevented.
A need exists for an effective mechanism for creating field effect transistor (FET) body connections. It is desirable to provide a way to create FET body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits.
A principal object of the present invention is to provide methods and apparatus for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. Other important objects of the present invention are to provide such methods and apparatus for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, methods and apparatus are provided for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The field effect transistor (FET) body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench isolation shape. The adjacent FET devices share a common diffusion area, such as source or drain. An underpath connecting bodies of the adjacent FET devices is formed by selectively spacing apart adjacent gate lines.
In accordance with features of the invention, the underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area. As a result an underpath body connection is formed. Such methods of building adjacent FET devices with an underpath connecting the two device bodies can be used in combination.